1 idt74fct16543at/ct/et fast cmos 16-bit latched transceiver industrial temperature range september 2009 industrial temperature range features: ? 0.5 micron cmos technology ? high-speed, low-power cmos replacement for abt functions ? typical t sk(o) (output skew) < 250ps ? low input and output leakage 1a (max.) ?v cc = 5v 10% ? high drive outputs (?32ma i oh , 64ma i ol ) ? power off disable outputs permit ?live insertion? ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c ? available in ssop, tssop, and tvsop packages functional block diagram the idt logo is a registered trademark of integrated device technology, inc. ? 2009 integrated device technology, inc. dsc-5444/5 idt74fct16543at/ct/et fast cmos 16-bit latched transceiver description: the fct16543t 16-bit latched transceivers are built using advanced dual metal cmos technology. these high-speed, low-power devices are organized as two independent 8-bit d-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. for example, the a-to-b enable (x ceab ) must be low in order to enter data from the a port or to output data from the b port. x leab controls the latch function. when x leab is low, the latches are transparent. a subsequent low-to-high transition of x leab signal puts the a latches in the storage mode. x oeab performs output enable function on the b port. data flow from the b port to the a port is similar but requires using x ceba , x leba , and x oeba inputs. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the fct16543t is ideally suited for driving high-capacitance loads and low-impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. c d 1 b 1 1 leab 1 ceab 1 oeab 1 leba 1 ceba 1 oeba to seven other channels 1 a 1 2 b 1 2 leab 2 ceab 2 oeab 2 leba 2 ceba 2 oeba to seven other channels 2 a 1 c d c d c d 56 54 55 1 3 2 5 29 31 30 28 26 27 15 52 42
2 industrial temperature range idt74fct16543at/ct/et fast cmos 16-bit latched transceiver pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to 7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxx output and i/o terminals. 3. outputs and i/o terminals for fct162xxx. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c out output capacitance v out = 0v 3.5 8 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. ssop/ tssop/ tvsop top view 1 b 1 1 b 2 gnd 1 b 3 1 b 4 v cc 1 b 5 1 b 6 1 oeba 1 b 7 1 b 8 2 b 1 2 b 2 gnd 2 b 3 2 b 4 v cc 2 b 5 gnd 2 b 7 2 b 6 2 b 8 gnd 2 oeba gnd 1 a 1 1 a 2 v cc 1 a 3 1 a 4 gnd 1 a 5 1 a 6 1 a 7 1 a 8 gnd 2 a 1 2 a 2 v cc 2 a 3 2 a 5 2 a 4 2 a 7 gnd 2 a 8 2 a 6 2 oeab 2 leab 2 ceab 1 ceab 1 leab 1 oeab 1 leba 1 ceba 2 leba 2 ceba 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 29 30 31 32 25 26 27 28 notes : 1. * before x leab low-to-high transition h = high voltage level l = low voltage level x = don?t care 2. a-to-b data flow shown; b-to-a flow control is the same, except using x ceba , x leba and x oeba . function table (1, 2) for a-to-b (symmetric with b-to-a) latch output inputs status buffers x ceab x leab x oeab xax to xbx xbx h x x storing z x h x storing x l l l transparent current a inputs l h l storing previous* a inputs l l h transparent z l h h storing z pin description pin names description x oeab a-to-b output enable input (active low) x oeba b-to-a output enable input (active low) x ceab a-to-b enable input (active low) x ceba b-to-a enable input (active low) x leab a-to-b latch enable input (active low) x leba b-to-a latch enable input (active low) x a x a-to-b data inputs or b-to-a 3-state outputs x b x b-to-a data inputs or a-to-b 3-state outputs
3 idt74fct16543at/ct/et fast cmos 16-bit latched transceiver industrial temperature range symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max. , v o = 2.5v (3) ?50 ? ?180 ma v oh output high voltage v cc = min. i oh = ?3ma 2.5 3.5 ? v v in = v ih or v il i oh = ?15ma 2.4 3.5 ? v i oh = ?32ma (4) 23?v v ol output low voltage v cc = min. i ol = 64ma ? 0.2 0.55 v v in = v ih or v il i off input/output power off leakage (5) v cc = 0v, v in = or v o 4.5v ? ? 1 a symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (input pins) (5) v cc = max. v i = v cc ??1a input high current (i/o pins) (5) ??1 i il input low current (input pins) (5) v i = gnd ? ? 1 input low current (i/o pins) (5) ??1 i ozh high impedance output current v cc = max. v o = 2.7v ? ? 1 a i ozl (3-state output pins) (5) v o = 0.5v ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?80 ?140 ?250 ma v h input hysteresis ? ? 100 ? mv i ccl quiescent power supply current v cc = max ? 5 500 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 10% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. this test limit for this parameter is 5a at t a = ?55c. output drive characteristics
4 industrial temperature range idt74fct16543at/ct/et fast cmos 16-bit latched transceiver power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply v cc = max. ? 0.5 1.5 ma current ttl inputs high v in = 3.4v (3) i ccd dynamic power supply current (4) v cc = max., outputs open v in = v cc ? 60 100 a / x ceab and x oeab = gnd v in = gnd mhz x ceba = v cc one input toggling 50% duty cycle i c total power supply current (6) v cc = max., outputs open v in = v cc ? 0.6 1.5 ma f i = 10mhz v in = gnd 50% duty cycle x leab , x ceab and x oeab = gnd v in = 3.4v ? 0.9 2.3 x ceba = v cc v in = gnd one bit toggling v cc = max., outputs open v in = v cc ? 2.4 4.5 (5) f i = 2.5mhz v in = gnd 50% duty cycle x leab , x ceab and x oeab = gnd v in = 3.4v ? 6.4 16.5 (5) x ceba = v cc v in = gnd sixteen bits toggling notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + i cc d h n t + i ccd (f cp n cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i
5 idt74fct16543at/ct/et fast cmos 16-bit latched transceiver industrial temperature range switching characteristics over operating range notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. 4. this limit is guaranteed but not tested. 74fct16543at 74fct16543ct 74fct16543et symbol parameter condition (2) min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 1.5 6.5 1.5 5.1 1.5 3.4 ns t phl transparent mode r l = 500 xax to xbx or xbx to xax t plh propagation delay 1.5 8 1.5 5.6 1.5 3.7 ns t phl x leba to xax, x leab to xbx t phz output enable time 1.5 9 1.5 7.8 1.5 4.8 ns t plz x oeba or x oeab to xax or xbx x ceba or x ceab to xax or xbx t pzh output disable time 1.5 7.5 1.5 6.5 1.5 4 ns t pzl x oeba or x oeab to xax or xbx x ceba or x ceab to xax or xbx t su set-up time high or low 2 ? 2 ? 1 ? ns xax or xbx to x leab or x leba t h hold time high or low 2 ? 2 ? 1 ? ns xax or xbx to x leab or x leba t w x leab or x leba pulse width low 4 ? 4 ? 3 (4) ?ns t sk(o) output skew (3) ? 0.5 ? 0.5 ? 0.5 ns
6 industrial temperature range idt74fct16543at/ct/et fast cmos 16-bit latched transceiver pulse generator r t d.u.t. v cc v in c l v out 50pf 500 500 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
7 idt74fct16543at/ct/et fast cmos 16-bit latched transceiver industrial temperature range ordering information xx temp. range xxxx device type xx package pvg pag pfg shrink small outline package - green thin shrink small outline package - green thin very small outline package - green 16-bit latched transceiver 74 40 c to +85 c 16 double-density, 5 volt, high drive fct xxx family 543at 543ct 543et corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com datasheet document history 09/28/09 pg. 7 updated the ordering information by removing the "idt" notation and non rohs part.
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